Xilinx AXI Chip2Chip for Multi-FPGA designThe AXI Chip2Chip IP from Xilinx allows the designer to connect two or more FPGAs using an AXI bus implemented using tranceivers running…Nov 21, 2020Nov 21, 2020
Xilinx MPSoC PS DDR Performance MonitorIf you are using Xilinx MPSoC devices, I think you need to know about the PS DDR AXI Performance Monitor. While this is not a new block, I…Nov 16, 20201Nov 16, 20201
RDMA from Xilinx FPGA to Nvidia GPUs — Part 1I have recently had the need to design a system concept able to process real-time video at a very high frame rate on a desktop PC.Nov 8, 20202Nov 8, 20202
